1. Field of the Invention
The present invention relates to methods and apparatus for compensating a solid state attenuator and more particularly to such methods and apparatus for compensating attenuators which incorporate resistive ladders in which selected legs of the ladder have preselected resistance values.
2. Description of the Related Art
In one type of prior art binarily weighted attenuator, an attenuator of the type known as an R-2R ladder is utilized in a fashion similar to a digital-to-analog converter. Such an attenuator is illustrated generally at 10 in FIG. 1 and includes therein a number of vertical branches, one of which is indicated generally at 12. Vertical branch 12 includes therein a resistor 14 having a value 2R. Commonly, such a resistor is made of NiCr and comprises two resistors in series, each having a value R. Vertical branch 12 further includes FETs 16, 18 with FET 16 having a source grounded as shown and FET 18 having a source connected to the input of a summing amplifier 20.
Attenuator 10 further includes a plurality of horizontal branches, one of which is indicated generally at 22. Included therein is a resistor 24 having a value R. As can be seen, there are a plurality of vertical branches, like branch 12, which are substantially identical to one another as well as a plurality of substantially identical horizontal branches, like branch 22, which connect the upper ends of adjacent pairs of vertical branches. A horizontal branch 25 includes therein a resistor 27, such having a resistance R. A termination branch 29 includes therein a resistor 31 also having a resistance R.
In operation, a selected bit value, which can assume one of two states, is associated with each vertical branch in attenuator 10. Conventional drive circuitry 11 switches adjacent switching devices responsive to the value of corresponding bits in a digital word. FETs 16, 18 in branch 12 are driven by conventional circuitry, drive circuits 11, complementary to one another and in response to the value of the bit associated with branch 12. In other words when the value of the bit associated with branch 12 is in one state, FET 16 is on and FET 18 is cut off. When the value of the bit is in its other state, FET 18 is on and FET 16 is cut off.
Current flowing in attenuator 10, in response to an input voltage applied to terminal V.sub.i, is split in halves at each 2R-R juncture as illustrated in FIG. 1. It can thus be seen that summing amplifier 20 produces a voltage at output terminal V.sub.o thereof which is attenuated by an amount related to the bit values associated with each of the vertical branches, like branch 12, in attenuator 10.
If it is assumed that the FETs in attenuator 10 have no resistance when biased to their conducting condition, the attenuator evenly splits the current at each juncture of a vertical and horizontal branch. Resistor 31 properly terminates the ladder in a conventional way by providing a total resistance of 2R in horizontal branch 25 and termination branch 29. Thus, 1/2 of the current flows into horizontal branch 25 and 1/2 into its related vertical branch, again assuming no FET resistance.
The prior art circuit of FIG. 1 suffers from several disadvantages. First, each FET has a finite resistance when biased into a conducting condition, thus increasing the value of the resistance in each vertical leg to something above 2R. It can be seen that in order to evenly split the current at the juncture of each vertical and horizontal branch, the total resistance presented by the circuit for each path must be equal. Because each FET, like FET 16, 18, presents a finite resistance when the FET is on, and one of the FETs is always on, the value of 2R may be slightly reduced in an effort to provide a total resistance for each vertical branch equal to 2R. This approach does not solve the problem, however, because the value of the resistance of each FET when conducting varies as a function of ambient temperature and of the particular process by which the FET was fabricated.
The tendency of the resistance of each FET when on to vary as a function of temperature and process contributes to differential errors, i.e., those which prevent the current from being evenly split at the juncture of each vertical and horizontal branch. This tendency also contributes to absolute errors, which affect the value of the impedance at the input of the attenuator.
Rather than adjusting the value of 2R in each vertical leg, the FETs can be made large so that the resistance of each FET while on is negligible. Doing so, however, increases the capacitance of each FET thus causing bandwidth problems at higher frequencies and also takes up a larger chip area.